Semiconductor processing for forming integrated circuits requires a series of processing steps. These processing steps include the deposition and patterning of material layers such as insulating layers, polysilicon layers, and metal layers. The material layers are typically patterned using a photoresist layer that is patterned over the material layer using a photomask or reticle. Typically, the photomask has alignment targets or keys that are aligned to fiduciary marks formed in the previous layer on the substrate. However, as the size of integrated circuit features continues to decrease, it becomes increasingly difficult to measure the overlay accuracy of one masking level to the previous level. This overlay metrology problem becomes particularly difficult at submicrometer feature sizes where overlay alignment tolerances are reduced to provide reliable semiconductor devices. One type of overlay measurement is known as diffraction based overlay metrology.
The overlay measurement problem is compounded when material layers are formed using more than two patterns, thereby producing a structure with multiple potential overlay errors. For example, a single layer may include two or three or more patterns produced by different reticles, with one or more overlying patterned layers, where each pattern must be accurately aligned with all other patterns. Alternatively, many layered patterns, more than two layers, may be formed with separate reticles, where again, each pattern must be accurately aligned with a preceding pattern. When three or more patterns are present, the alignment between each pattern must be measured resulting in two or more overlay error measurements. Conventionally, to measure multiple overlay errors, a separate set of targets is generated for each individual overlay error and the overlay errors are separately measured. Consequently, a large foot print is required for the large number of targets and throughput is reduced due to the number of separate measurements required.